NOTE: Click STOP first, then START to start the animation.
This simulation shows the inner workings of how the cache memory interacts with the CPU and the main memory. The applet seen below is set out with a CPU at the top, the cache in the middle and the main memory at the bottom. In this simulation it shows the process of the CPU getting a section of data.
The process starts with a request address being sent to the cache controller. The cache controller now checks its frames to see if any of the tags match the address. If the correct match is found the data from corresponding frame is sent back to the CPU. In the case where there are no tag matches found the address of the data is collected from the main memory. When this case occurs the cache is updated with the value and with an empty frame being used if possible. In the case of no empty frames being available then a frame is selected at random. In this simulation data being sent or components that are being probed are illustrated with the movement of red circles and data being stored in the cache frames is illustrated with the grey boxes turning green. When the CPU requests a piece of data the request counter increases by one count. When a piece of data is collected from the main memory the access counter increases by one count. If the data is successfully found in the cache frames then the hit counter will increase by one.
Stages of animation
1. The request address 2 is sent from the CPU to the cache controller. Now the cache controller is probed and no tag is found with a match of 2.
2. The request address 2 is now sent to the main memory where the data is collected and sent back to the CPU but is also stored in the cache frames with the tag changing to the value 2.
3. Now the CPU sends a request address 8 to the cache controller and the previous two stages are repeated with the tag turning to 8. This is due to fact that 8 is not a tag in the cache frames.
4. The CPU next sends request address 2 to the cache controller. When the cache frames are probed it can be seen that the request address 2 is a tag for a cache frame. The data is now sent from this frame to the CPU and because of this there is no need for the main memory to be probed. To finish off the CPU sends a final request address 13 to the cache controller and step 1 and 2 are repeated with the tag changing to 13. This is because 13 is not a tag in the cache frame.